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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. tft-lcd supply + dcp + vcom amplifier + gate pulse modulator + reset isl97649a the isl97649a is an integrated power management ic (pmic) for tft-lcds used in notebooks, tablet pcs, and monitors. the device integrates a boost converter for generating a vdd , an ldo for vlogic. von and voff are generated by a charge pump driven by the switch node of the boost. the isl97649a also includes a v on slice circuit, reset function, and a high performance vcom amplifier with dcp (digitally cont rolled potentiometer) that is used as a vcom calibrator. the avdd boost converter features a 1.5a/0.18 boost fet with 600/1200khz switching frequency. the logic ldo includes a 350ma fet for driving the low voltage needed by external digital circuitry. the gate pulse modulator can control the gate voltage up to 30v, and both the rate and slew delay times are selectable. the supply monitor generates a rese t signal when the system is powered down. it provides a programmable vcom with i 2 c interface. one vcom amplifier is also integrated in the chip. the output of the vcom is powered up with the voltage at the last programmed 8-bit eeprom setting. features ? 2.5v to 5.5v input ? 1.5a integrated boost for up to 15v a vdd ?v on /v off supplies generated by charge pumps driven by the boost switch node ? ldo for vlogic channel ? 600/1200khz selectable switching frequency ? integrated gate pulse modulator ? reset signal generated by supply monitor ? integrated vcom amplifier ?dcp -i 2 c serial interface, address: 0101000, msb left - wiper position stored in 8-bit nonvolatile memory and recalled on power-up - endurance, 1,000 data changes per bit ? uvlo, uvp, ovp, ocp, and otp protection ? pb-free (rohs compliant) ? 28 ld 4x5 qfn applications ? lcd notebook, tablet, and monitor pin configuration isl97649a (28 ld 4x5 qfn) top view en lx vin freq comp ss gpm_lo avdd scl sda pos rset fb pgnd ce re vgh vghm vflk l_in cd2 l_out reset adj vdiv neg 1 2 3 4 5 6 7 22 21 20 19 18 17 16 28 27 26 25 24 23 9 1011121314 vdpm 8 vout 15 gnd thermal pad december 5, 2011 fn7928.0
isl97649a 2 fn7928.0 december 5, 2011 application diagram l_in lx fb comp pgnd vlogic avdd avdd vin vin scl sda adj avdd boost controller ldo gpm vflk vgh vgh gpm en dcp vghm avdd pos out vcom rset avdd sw avdd von sw freq sequencer re voff vcom op ss l_out ce vdpm gpm_lo voltage detector avdd v in v in vdiv cd2 reset reset ldo vin neg thermal pad vlogic vlogic l1 10h c4, 5, 6 30f r1 73.2k r2 8.06k c20 15nf r12 5.5k c17 1nf c14 100pf r5 100k c18 0.47f r14 85k r15 115k open c26 1nf r16 10k c11 0.1f c10 47nf c8 47nf c9 1f c12 1f c28 0.1f c15 1f c16 1f vgh r26 100k r22 22k c1, 2 20f c25 1f c24 2.2f r17 8.25k r18 3.92k r9 10k 133k r8 r7 83k c19 0.47uf r6 1k c32 0.1f d1 d4 d2 d3 z1 q1 c7 0.1f
isl97649a 3 fn7928.0 december 5, 2011 pin descriptions pin# symbol description 1 fb avdd boost converter feedback . connect to the center of a voltage divider between avdd and gnd to set the avdd voltage. 2pgndpower ground 3 ce gate pulse modulator delay control. connect a capacitor between this pin and gnd to set the delay time. 4 re gate pulse modulator slew control. connect a resistor between this pin and gnd to set the falling slew rate. 5 vgh gate pulse modulator high voltage input. place a 0.1f decoupling capacitor close to the vgh pin. 6 vghm gate pulse modulator output for gate driver ic 7 vflk gate pulse modulator control input from t con 8 vdpm gate pulse modulator enable. connect a capacitor from vdpm to gnd to set the delay time befo re gpm is enabled. a current source charges the capacitor on vdpm. 9 gpm_lo gate pulse modulator low voltage input; place a 0.47f decoupling capacitor close to the gpm_lo pin. 10 avdd dcp and vcom amplifier high voltage analog supply; pl ace a 0.47f decoupling capacitor close to the avdd pin. 11 scl i 2 c comparable clock input 12 sda i 2 c compatible serial bidirectional data line 13 pos vcom positive amplifier non-inverting input 14 rset dcp sink current adjustment pin; connect a resistor between this pin and gnd to set the resolution of the dcp output volt age. 15 vout vcom amplifier output 16 neg vcom negative amplifier non-inverting input 17 vdiv voltage detector threshold. connect to the center of a resistive divider between v in and gnd. 18 adj vlogic ldo feedback. connect to the center of a resistive divider between l_out and gnd to set v logic voltage for t con . 19 reset voltage detector reset output 20 l_out ldo output. connect at least one 1f capacitor to gnd for stable operation. 21 cd2 voltage detector rising edge delay. connect a capacitor between this pin and gnd to set the rising edge delay. 22 l_in ldo input. connect a 1f decoup ling capacitor close to this pin. 23 ss boost converter soft-start. connect a capacitor be tween this pin and gnd to set the soft-start time. 24 comp boost converter compensation pin. connect a series resistor and capacitor between this pin and gnd to optimize transient response and stability. 25 freq boost converter frequency select; pull it to logic high to operate boost at 1.2mhz. connect this pin to gnd to operate bo ost at 600khz. 26 vin ic input supply. connect a 0.1f decoupling capacitor close to this pin. 27 lx avdd boost converter switching node 28 en avdd enable pin ordering information part number (notes 2, 3) part marking v in range (v) temp range (c) package (pb-free) pkg. dwg. # isl97649airz (note 1) 97649 airz 2.5 to 5.5 -40 to +85 28 ld 4x5 qfn l28.4x5a ISL97649AIRTZ-EVALZ isl97649a evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl97649a for more information on msl please see techbrief tb363 .
isl97649a 4 fn7928.0 december 5, 2011 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial interface specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 rectifier diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 linear regulator (ldo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 supply monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 gate pulse modulator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 vcom amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 dcp memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 protocol conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 communication with isl97649a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 register description: access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 register description: ivp and wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 initial vcom setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 isl97649a i2c eeprom reading/writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
isl97649a 5 fn7928.0 december 5, 2011 absolute maximum rating s thermal information re, vghm, gpm_lo and vgh to gnd . . . . . . . . . . . . . . . . . . . . -0.3 to +36v lx, avdd, pos, out to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18v voltage between gnd and pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5v all other pins to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101). . . . . . . . . . . . . . . 1kv thermal resistance (typical) ja (c/w) jc (c/w) 28 ld 4x5 qfn package (notes 4, 5). . . . . 38 4.5 ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c functional junction temperature . . . . . . . . . . . . . . . . . . . .-40c to +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature during soldering . . . . . . . . . . . . . . . . . . . . . . . . +260c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = enable = 3.3v, a vdd =8v, v ldo = 2.5v, v on =24v, v off = - 6v. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 6) typ (note 7) max (note 6) units general vin v in supply voltage range 2.5 3.3 5.5 v i s_dis v in supply currents when disabled vin < uvlo 390 500 a i s v in supply currents enable = 3.3v, overdrive avdd and vgh 0.7 1.0 ma i ebable enable pin current enable = 0v 0 a logic input characteristics - enable, flk, scl, sda, freq v il low voltage threshold 0.65 v v ih high voltage threshold 1.75 v r il pull-down resistor enable, flk, freq 0.85 1.25 1.65 m internal oscillator f osc switching frequencies freq = low, t a = +25c 550 600 650 khz freq = high, t a = +25c 1100 1200 1300 khz avdd boost regulator davdd/ diout avdd load regulation 50ma < i load < 250ma 0.2 % davdd/ dvin avdd line regulation i load = 150ma, 2.5v < v in < 5.5v 0.15 % v fb feedback voltage (v fb )i load = 100ma, t a = +25c 0.792 0.8 0.808 v i fb fb input bias current 100 na r ds(on) switch on-resistance t a = +25c 180 230 m i lim switch current limit 1.125 1.5 1.875 a d max max duty cycle freq = 1.2mhz 80 90 % eff freq = 1.2mhz, iavdd = 100ma 91 %
isl97649a 6 fn7928.0 december 5, 2011 ldo regulator dv ldo / dv in line regulation ildo = 1ma, 3.0v < v in1 < 5.5v 1 mv/v dv ldo / di out load regulation 1ma < ildo < 350ma 0.2 % v do dropout voltage output drops by 2%, ildo = 350ma 225 300 mv i liml current limit output drops by 5% 330 425 ma v adj adj reference voltage i load = 50ma, t a = +25c 0.792 0.8 0.808 v i adj adj input bias current 0.1 a gate pulse modulator v gh vgh voltage 733 v v ih_vdpm v dpm enable threshold 1.13 1.215 1.30 v i vgh vgh input current vflk = 0 125 a re = 100k ? , vflk = vin 27.5 a v gpm_lo gpm_lo voltage 2vgh-2 v i gpm_lo vgpm_lo input current -2 0.1 2 a vce th1 ce threshold voltage 1 0.6xvin 0.8xvin v vce th2 ce threshold voltage 2 1.215 v i ce ce current 100 a r vghm_pd vghm pull-down resistance 1.1 k r onvgh vgh to vghm on resistance 23 idpm vdpm charge current 10 a supply monitor v ih_vdiv vdiv high threshold vdiv rising 1.265 1.280 1.295 v v il_vdiv vdiv low threshold vdiv falling 1.21 1.222 1.234 v vth cd2 cd2 threshold voltage 1.200 1.217 1.234 v i cd2 cd2 charge current 10 a r il_reset reset pull-down resistance 650 t delay_reset reset delay on the rising edge 121.7k* cd s vcom amplifier r load =10k, c load =10pf, unless otherwise stated i s_com vcom amplifier supply current 0.7 1.08 ma v os offset voltage 2.5 15 mv i b non-inverting input bias current 0na cmir common mode input voltage range 0avdd v cmrr common-mode rejection ratio 60 75 db psrr power supply rejection ratio 70 85 db v oh output voltage swing high i out (source) = 0.1ma avdd - 1.39 mv i out (source) = 75ma avdd - 1.27 v v ol output voltage swing low i out (sink) = 0.1ma 1.2 mv i out (sink) = 75ma 1 v electrical specifications v in = enable = 3.3v, a vdd =8v, v ldo = 2.5v, v on =24v, v off = - 6v. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 6) typ (note 7) max (note 6) units
isl97649a 7 fn7928.0 december 5, 2011 i sc output short circuit current pull-up 150 225 ma pull-down 150 200 ma sr slew rate 25 v/s bw gain bandwidth -3db gain point 20 mhz digital controlled potentiometer set vr (note 12) set voltage resolution 8bits set dnl (note 8, 9, 14) set differential nonlinearity t a = +25c 1 lsb set zse (note 10, 14) set zero-scale error t a = +25c 2 lsb set fse (note 11,14) set full-scale error t a = +25c 8 lsb i rset rset current 100 a avdd to set avdd to set voltage attenuation 1:20 v/v fault detection threshold v uvlo undervoltage lock out threshold pv in rising 2.25 2.33 2.41 v pv in falling 2.125 2.20 2.27 v ovp avdd (note 13) boost overvoltage protection off threshold to shutdown ic 15.0 15.5 16.0 v t off thermal shut-down all channels temperature rising 153 c power sequence timing t ss vlogic vlogic soft-start time 0.45 ms i ss boost soft-start current 3 5.5 8 a electrical specifications v in = enable = 3.3v, a vdd =8v, v ldo = 2.5v, v on =24v, v off = - 6v. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 6) typ (note 7) max (note 6) units serial interface specifications for scl and sda unless otherwise noted. symbol parameter test conditions min (note 14) typ (note 7) max (note 14) units f scl (note 6) scl frequency 400 khz t in (note 6) pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v in , until sda exits the 30% to 70% of v in window 480 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v in during the following start condition 480 ns t low clock low time measured at the 30% of v in crossing 480 ns t high clock high time measured at the 70% of v in crossing 400 ns t su:sta start condition set-up time scl rising edge to sda falling edge; both crossing 70% of v in 480 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v in to scl falling edge crossing 70% of v in 400 ns
isl97649a 8 fn7928.0 december 5, 2011 t su:dat input data set-up time from sda exiting the 30% to 70% of v in window, to scl rising edge crossing 30% of v in 40 ns t hd:dat input data hold time from scl rising edge crossing 70% of v in to sda entering the 30% to 70% of v in window 0ns t su:sto stop condition set-up time from scl rising edge crossing 70% of v in , to sda rising edge crossing 30% of v in 400 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge; both crossing 70% of v in 400 ns c scl capacitive on scl 5pf c sda capacitive on sda 5pf t wp non-volatile write cycle time 25 ms eeprom endurance t a = +25c 1 kcyc eeprom retention t a = +25c 88 khrs notes: 6. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. 7. typical values are for t a = +25c and v in = 3.3v. 8. lsb = i v 255 - v 1 i / 254. v 255 and v 1 are the measured voltages for the dcp register set to ff hex and 01 hex respectively. 9. dnl = i v i+1 - v i i / lsb-1, 10. zs error = (v 1 -vmin) / lsb. vmin = (vavdd*r2) * [1-254*r1/(255*20*rset)]/ (r1+r2). 11. fs error = (v 255 - vmax) / lsb. vmax= (vavdd*r2) * [1-0*r1/(255*20*r set)]/ (r1+r2). 12. established by design. not a parametric spec. 13. boost will stop switching as soon as boost output reaches ovp threshold. 14. compliance to limits is assure d by characterization and design. serial interface specifications for scl and sda unless otherwise noted. (continued) symbol parameter test conditions min (note 14) typ (note 7) max (note 14) units i 1 255 , []
isl97649a 9 fn7928.0 december 5, 2011 typical performance curves figure 1. avdd efficiency vs i avdd figure 2. i avdd load regulation vs i avdd figure 3. i avdd line regulation vs v in figure 4. boost converter transient response figure 5. gpm circuit waveform figure 6. gpm circuit waveform 76 78 80 82 84 86 88 90 92 0.0 50 100 150 200 250 300 350 i avdd (ma) v in = 3.3v, v out = 8.06v efficiency (%) f osc = 600khz f osc = 1.2mhz -0.04 -0.03 -0.02 -0.01 0.00 50 100 150 200 250 i avdd (ma) load regulation (%) f osc = 600khz f osc = 1.2mhz v in = 3.3v, v out = 8.06v 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v in (v) a vdd (v) i avdd = 150ma l = 10h, c out = 40f, c comp = 15nf, r comp = 5.5k ce = 1pf, re = 100k vghm ce = 100pf, re = 100k vghm
isl97649a 10 fn7928.0 december 5, 2011 figure 7. gpm circuit waveform figure 8. gpm circuit waveform figure 9. v ghm follows v gh when the system powers off figure 10. vcom rising slew rate figure 11. ldo line regulation vs v in figure 12. ldo load regulation vs i ldo typical performance curves (continued) ce = 10pf, re = 50k vghm ce = 10pf, re = 150k vghm vghm 2.4836 2.4838 2.4840 2.4842 2.4844 2.4846 2.4848 2.4850 2.4852 2.4854 3.0 3.5 4.0 4.5 5.0 5.5 vldo_in (v) vildo (v) ildo = 1ma -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0 50 100 150 200 250 300 350 ildo (ma) load regulation (%) vldo = 2.5v
isl97649a 11 fn7928.0 december 5, 2011 applications information enable control with vin > uvlo, only the logic output channel is activated. all other functions in isl97649a are shut down when the enable pin is pulled down. when the voltage at the enable pin reaches h threshold, the whole chip turns on. frequency selection the isl97649a switching frequency can be user selected to operate at either constant 600khz or 1.2mhz. lower switching frequency can save power dissipation at very light load conditions. also, low switching frequency more easily leads to discontinuous conduction mo de, while higher switching frequency allows for smaller external components, such as inductor and output capacitors, etc. higher switching frequency will get higher efficiency within some loading range depending on vin, vout, and external components, as shown in figure 1. connecting the freq pin to gnd sets the pwm switching frequency to 600khz, or co nnecting freq pin to v in for 1.2mhz. soft-start the soft-start is provided by an internal current source to charge the external soft-start capacitor. the isl97649a ramps up the current limit from 0a up to the full value, as the voltage at the ss pin ramps from 0v to 0.8v. hence, the soft-start time is 3.2ms when the soft-start capacitor is 22nf, 6.8ms for 47nf and 14.5ms for 100nf. operation the boost converter is a current mode pwm converter operating at either 600khz or 1.2mhz. it ca n operate in both discontinuous conduction mode (dcm) at light load and continuous conduction mode (ccm). in continuous conduction mode, current flows continuously in the inductor duri ng the entire switching cycle in steady state operation. the voltage conversion ratio in continuous current mode is given by equation 1: where d is the duty cycle of the switching mosfet. the boost regulator uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. a comp arator looks at the peak inductor current cycle-by-cycle and terminates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 60k ? is recommended. the boost converter output voltage is determined by equation 2: the current through the mosfet is limited to 1.5a peak . this restricts the maximum outp ut current (average) based on equation 3: where i l is the peak-to-peak inductor ripple current, and is set by equation 4: where f s is the switching frequency (600khz or 1.2mhz). capacitor an input capacitor is used to suppress the voltage ripple injected into the boost converter. the ceramic capacitor with a capacitance larger than 10f is recommended. the voltage rating of the input capacitor shou ld be larger than the maximum input voltage. some input capacitors are recommended in table 1. inductor the boost inductor is a critical part that influences the output voltage ripple, transient respon se, and efficiency. values of 3.3h to 10h are used to match the internal slope compensation. the inductor must be able to handle the following average and peak currents shown in equation 5: some inductors are recommended in table 2 for different design considerations. rectifier diode a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the reverse voltage rating of this diode should be higher than the maximum output voltage. the rectifier diode must meet the output current and peak inductor current requirements. table 3 shows some recommendations for boost converter diode. v boost v in ----------------- 1 1d ? ------------ - = (eq. 1) v boost r 1 r 2 + r 2 -------------------- v fb = (eq. 2) table 1. boost converter input capacitor recommendation capacitor size mfg part number 10f/6.3v 0603 tdk c1608x5r0j106m 10f/16v 1206 tdk c3216x7r1c106m 10f/10v 0805 murata grm21br61a106k 22f/10v 1210 murata grb32er61a226k table 2. boost converter inductor recommendation inductor dimensions (mm) mfg part number note 10h/ 4apeak 8.3x8.3x4.5 sumida cdr8d43-100nc efficiency optimization 6.8h/ 1.8apeak 5.0x5.0x2.0 tdk plf5020t-6r8m1r8 i omax i lmt i l 2 -------- ? ?? ?? v in v o -------- = (eq. 3) i l v in l -------- d f s --- - = (eq. 4) i lavg i o 1d ? ------------ - = i lpk i lavg i l 2 -------- + = (eq. 5)
isl97649a 12 fn7928.0 december 5, 2011 output capacitor the output capacitor supplies the load directly and reduces the ripple voltage at the output. output ripple voltage consists of two components: 1. the voltage drop due to the inductor ripple current flowing through the esr of the output capacitor. 2. charging and discharging of the output capacitor. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capa citor should be greater than the maximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. c out in equation 6 assumes the effective value of the capacitor at a particular voltage and not the manufacturer?s stated value, measured at 0v. table 4 shows some selections of output capacitors. compensation the boost converter of isl97649a can be compensated by an rc network connected from the comp pin to ground. 15nf and 5.5k rc network is used in the demo board. the larger value resistor and lower value capacitor can lower the transient overshoot, however, at the expense of the stability of the loop. linear regulator (ldo) the isl97649a includes an ldo wi th adjustable output. it can supply current up to 350ma. the output voltage is adjusted by connection of the adj pin. the efficiency of the ldo depends on the difference between input voltage and output voltage (equation 7) by assuming ldo quiescent current is much lower than ldo output current: the less difference between input and output voltage, the higher efficiency it is. ceramic capacitors are recommended for the ldo input and output capacitors. intersil recommends an output capacitor within the 1f to 4.7f range and a maximum feedback resistor impedance of 20k ? . larger capacitors help to reduce noise and deviation during transient load change. some capacitors are recommended in table 5. supply monitor circuit the supply monitor circuit monitors the voltage on vdiv, and sets open-drain output reset low when vdiv is below 1.28v (rising) or 1.22v (falling). there is a delay on the rising edge, controlled by a capacitor on cd2. when vdiv exceeds 1.28v (rising), cd2 is charged up from 0v to 1.217v by a 10a current source. once cd2 exceeds 1.217v, reset will go tri-state. when vdiv falls below 1.22v, reset will become low with a 650 ? pull-down resistance. the delay time is controlled by equation 8: for example, the delay time is 12.17ms if the cd2 = 100nf. figure 13 shows the supply mo nitor circuit timing diagram. 10uh/ 2.2apeak 6.6x7.3x1.2 cyntec pcme061b-100ms pcb space/profile optimization table 3. boost converter rectifier diode recommendation diode v r /i avg rating package mfg pmeg2010er 20v/1a sod123w nxp mss1p2u 20v/1a microsmp vishay table 4. boost output capacitor recommendation capacitor size mfg part number 10f/25v 1210 tdk c3225x7r1e106m 10f/25v 1210 murata grm32dr61e106k table 2. boost converter inductor recommendation inductor dimensions (mm) mfg part number note v ripple i lpk esr v o v in ? v o --------------------- i o c out ------------- 1 f s --- - + = (eq. 6) table 5. ldo output capacitor recommendation capacitor size mfg part number 1f/10v 0603 tdk c1608x7r1a105k 1f/6.3v 0603 murata grm188r70j105k 2.2f/6.3v 0603 tdk c1608x7r0j225k % () v ldo_in v ldo_out ------------------------- ?? ?? ?? 100% = (eq. 7) t delay 121.7k cd2 = (eq. 8) vdiv reset 1.28v 1.22v 1.217v cd2 reset delay time is controlled by cd2 capacitor figure 13. supply monitor circuit timing diagram
isl97649a 13 fn7928.0 december 5, 2011 gate pulse modulator circuit the gate pulse modulator circuit functions as a three way multiplexer, switching vghm between ground, gpm_lo and vgh. voltage selection is provided by digital inputs vdpm (enable) and vflk (control). high to low delay and slew control is provided by external components on pins ce and re, respectively. when vdpm is low, the block is disabled and vghm is grounded. when the input voltage exceeds uvlo threshold, vdpm starts to drive an external capacitor. once vdpm exceeds 1.215v, the gpm circuit is enabled, and the output vghm is determined by vflk, reset signal and vgh voltage. if reset signal is high and vflk is high, vghm is pulled to vgh. when vflk goes low, there is a delay controlled by capacitor ce, following which, vghm is driven to gpm_lo, with a slew rate controlled by resistor re. note that gpm_lo is used only as a reference voltage for an amplifie r, and thus does not have to source or sink a significant dc current. low to high transition is determined primarily by the switch resistance and the external capaciti ve load. high to low transition is more complex. take the case where the block is already enabled (vdpm is h). when vflk is h, if ce is not externally pulled above threshold voltage 1, pin ce is pulled low. on the falling edge of vflk, a current is passed into pin ce to charge the external capacitor up to threshold voltage 2, providing a delay which is adjustable by varying the capacitor on ce. once this threshold is reached, the output starts to be pulled down from vgh to gpm_lo. the maximum slew current is equal to 500/(re + 40k), and the dv/dt slew rate is isl/c load , where c load is the load capacitance applied to vghm. the slew rate reduces as vghm approaches gpm_lo. if ce is always pulled up to a voltage above threshold 1, zero delay mode is selected; thus, there will be no delay from flk falling to the point where vghm starts to fall. slew down currents will be identical to the previous case. at power-down, when vin falls to uvlo, vghm will be tied to vgh until the vgh voltage falls to 3v. once the vgh voltage falls below 3v, vghm will not be actively driven until vin is driven. figure 14 shows the vghm voltage based on v in , vgh and reset. vcom amplifier the vcom amplifier is designed to control the voltage on the back plane of an lcd display. this plane is capacitively coupled to the pixel drive voltage, which alternatel y cycles positive and negative at the line rate for the display. thus, the amplifier must be capable of sourcing and sinking pulses of current, which can occasionally be quite large (in the range of 100ma for typical applications). the isl97649a vcom amplifier's output current is limited to 225ma typical. this limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. it does not necessarily prevent a large temperature rise if the current is maintained. (in this case, the whole chip may be shut down by the thermal trip to protect functionality.) if the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. this will happen in the s time scale in practical systems and for pulses 2 or 3 times the current limit; the vcom voltage will have settled again before the next line is processed. dcp memory description the isl97649a contains one non-volatile byte known as the initial value register (ivr). it is accessed by the i 2 c interface operations with address 00h. the ivr contains the value that is loaded into the volatile wiper register (wr) at power-up. the volatile wr and the non-vola tile ivr of a dcp are accessed with the same address. the access control register (acr) determines which word at address 00h is accessed (ivr or wr). the volatile acr must be set as follows: when the acr is all zeroes, whic h is the default at power-up: ? a read operation to address 0 outputs the value of the non-volatile ivr. vgh_m is forced to vgh when reset goes to low and vgh>3v power on delay time is controlled by c dpm slope is controlled by re delay time is controlled by ce figure 14. gate pulse modulator timing diagram vin uvlo 0 vgh reset vdpm vflk vghm threshold vgh gpm_lo power-on delay time controlled by c dpm slope is controlled by re delay time is controlled by ce vghm is forced to vgh when vin 1.215v falls to uvlo and vgh>3v
isl97649a 14 fn7928.0 december 5, 2011 ? a write operation to address 0 writes the identical values to the wr and ivr of the dcp. ? when the acr is 80h: - a read operation to addre ss 0 outputs the value of the volatile wr. - a write operation to address 0 only writes to the volatile wr. it is not possible to write to an ivr without writing the same value to its wr. 00h and 80h are the only values that should be written to address 2. all other values are reserved and must not be written to address 2. i 2 c serial interface the isl97649a supports a bidirectional bus oriented protocol. the protocol defines any device that sends data on to the bus as a transmitter and the receiving devi ce as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the dcp of the isl97649a operates as a slave device in all applications. the fall and rise time of sda and scl signal should be in the range listed in table 8. capacitive load on i 2 c bus is also specified in table 8. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line ca n change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 15). on power-up of the isl97649a, the sda pin is in the input mode. all i 2 c interface operations must be gin with a start condition, which is a high to low transition of sda while scl is high. the dcp continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 15) . a start condition is ignored during the power-up sequence and during internal non-volatile write cycles. all i 2 c interface must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 15). a stop condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. a stop condition during a write operation to a non-volatile writ e byte, initiates an internal non-volatile write cycle. the device enters its standby state when the internal non-volatile write cycle is completed. an ack (acknowledge) is a software convention used to indicate a successful data transfer. the transm itting device, either master or slave, releases the sda bus after tr ansmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the ei ght bits of data (see figure 16). the isl97649a dcp responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful receipt of an address byte. the isl97649a also respond with an ack after re ceiving a data byte of a write operation. the master must respond with an ack after receiving a data byte of a read operation. a valid identification byte contains 0101000 as the seven msbs. the lsb is in the read/write bit. its value is "1" for a read operation, and "0" for a write operation (see table 7). write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition (see figure 17). afte r each of the three bytes, the isl97649a responds with an ack. at this time, if the data byte is to be written only to volatile registers, the device enters its standby state. if the data byte is to be written also to non-volatile memory, the isl97649a begins its internal write cycle to non-volatile memory. during the in ternal non-volatile write cycle, the device ignores transitions at the sda and scl pins and the sda output is at high impedance state. when the internal non-volatile write cycle is completed, the isl97649a enters its standby state. the byte at address 02h determines if the data byte is to be written to volati le and/or non-volatile memory. data protection a stop condition also acts as a protection of non-volatile memory. a valid identification byte, address byte, and total number of scl pulses act as a pr otection of both volatile and non-volatile registers. during a write sequence, the data byte is loaded into an internal shift regi ster as it is received. if the address byte is 0 or 2, the data byte is transferred to the wiper register (wr) or to the access control register respectively, at the falling edge of the scl pulse that loads the last bit (lsb) of the data byte. if the address byte is 0, and the access control register is all zeros (default), then the stop condition initiates the internal write cycle to non-volatile memory. table 6. memory map address non-volatile volatile 2-acr 1 reserved 0ivrwr wr: wiper register, ivr: initial value register. table 7. identification byte format 0 101000 r/w (msb) (lsb) table 8. i 2 c interface specification parameter min typ max units sda and scl rise time 1000 ns sda and scl fall time 300 ns i 2 c bus capacitive load 400 pf
isl97649a 15 fn7928.0 december 5, 2011 figure 15. valid data changes, start, and stop conditions figure 16. acknowledge response from receiver figure 17. byte write sequence figure 18. read sequence sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the isl97649a a c k 00 11 a c k write signal at sda 0000 00 000 0 0 x signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 00 11 s t o p a c k 01 0 11 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 00 0 000 00 000 0 00 x
isl97649a 16 fn7928.0 december 5, 2011 read operation a read operation consists of a three-byte instruction followed by one or more data bytes (see figure 18). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to "0", an address byte, a second start, and a second identi fication byte with the r/w bit set to "1". after each of the th ree bytes, the isl97649a responds with an ack; then the isl97649a transmits the data byte. the master then terminates the re ad operation (i ssuing a stop condition) following the last bit of the data byte (see figure 16). the byte at address 02h determines if the data bytes being read are from volatile or non-volatile memory. communication with isl97649a there are three register addresses in the isl97649a, of which two can be used. address 00h and address 02h are used to control the device. address 01h is reserved and should not be used. address 00h contains the non-volatile initial value register (ivr), and the volatile wiper regi ster (wr). address 02h contains only a volatile word and is used as a pointer to either the ivr or wr. register description: access control the access control register (acr) is volatile and is at address 02h. it is 8 bits, and only the msb is significant; all other bits should be zero (0). the acr controls which word is accessed at register 00h as follows: ? 00h = nonvolatile ivr ? 80h = volatile wr all other bits of the acr should be written 0 or 1. power-up default for this address is 00h. register description: ivp and wr the output of the dcp is controlled directly by the wr. writes and reads can be made directly to this register to control and monitor without any non-volatile memory changes. this is done by setting address 02h to data 80h, then writing the data. the non-volatile ivr stores the power-up value of the dcp output. on power -up, the contents of the ivr are transferred to the wr. to write to the ivr, first address 02h is set to data 00h and then the data is written. writing a new value to the ivr register will set a new power- up position for the wiper. also, writing to this register will load the same value into the wr as the ivr. therefore, if a new value is loaded into the ivr, not only will the non-volatile ivr change, but the wr will also contain the same value after the write, and the wipe r position will change. reading from the ivr will not change the wr, if its contents are different. writing ? a ? new ? value ? to ? the ? ivr write ? to ? acr ? first 01010000a00000010a00000000a then, ? write ? to ? ivr 01010000a00000000ad0d7d6d5d4d3d2d1a note ? that ? the ? wr ? will ? also ? reflect ? this ? new ? value ? since ? both ? registers ? get ? writen ? at ? the ? same ? time d0:lsb, ? d7:msb writing ? a ? new ? value ? to ? wr ? only write ? to ? acr ? first 01010000a00000010a10000000a then, ? write ? to ? wr 01010000a00000000ad0d7d6d5d4d3d2d1a note ? that ? the ? ivr ? value ? will ? not ? change d0:lsb, ? d7:msb reading ? from ? ivr write ? to ? the ? acr ? first 01010000a00000010a00000000a then ? set ? the ? ivr ? address 01010000a00000000a read ? from ? the ? ivr 01010001ad0d7d6d5d4d3d2d1 example ? 2 reading ? from ? the ? wr write ? to ? the ? acr ? first 01010000a00000010a10000000a then ? set ? the ? wr ? address 01010000a00000000a read ? from ? the ? wr 01010001ad0d7d6d5d4d3d2d1
isl97649a 17 fn7928.0 december 5, 2011 initial vcom setting a 256-step resolution is provided under digital control, which adjusts the sink current of the ou tput. the output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current. the equation s that control the output are given in the following. the initial setting value is at 128. the wr value is set back to 128 if any error occurs during i 2 c read or write communication. when writing to the eeprom, vgh needs to be higher than 12v when avdd is 8v. outside these conditions, writing operations may be not successful. the maximum resistor value of rset is determined by the following equations: where r l , r u and rset in equation 11 correspond to r 7 , r 8 and r 9 in the application diagram on page 2. start-up sequence when vin rising exceeds uvlo, it takes 120s to read the settings stored in the chip in orde r to activate the chip correctly. after all the settings are written in the registers, vlogic starts up with a 0.5ms soft-start time. when both vlogic is in regulation and en is high, the boost converter starts up. the gate pulse modulator output vghm is held low until vdpm is charged to 1.215v. the detailed power on sequence is shown in figure 19. layout recommendation the device's performance, including efficiency, output noise, transient response and control loop stability, is affected by the pcb layout. pcb layout is critical, especially at high switching frequency. following are some general guidelines for layout: 1. place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v dc and v ref bypass capacitors close to the pins. 3. loops with large ac amplitudes and fast slew rate should be made as small as possible. 4. the feedback network should sense the output voltage directly from the point of load, and be as far away from the lx node as possible. 5. the power ground (pgnd) should be connected at the isl97649a exposed die plate area. 6. the exposed die plate, on the underside of the package, should be soldered to an equivalent area of metal on the pcb. this contact area should have multiple via connections to the back of the pcb as well as connections to intermediate pcb layers, if available to maximize thermal dissipation away from the ic. 7. to minimize the thermal resistance of the package when soldered to a multi-layer pcb, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissi pation to the surrounding air. 8. minimize feedback input track lengths to avoid switching noise pick-up. a demo board is available to illustrate the proper layout implementation. rset v_avdd 100 a ? < (eq. 9) iout 255 setting ? 255 ------------------------------------- v avdd 20 rset () -------------------------- - ? = (eq. 10) vout r l v avdd ? r u r l + () ---------------------------- 1 255 setting ? 255 ------------------------------------- r u 20 rset () -------------------------- - ? ?? ?? ? = (eq. 11)
isl97649a 18 fn7928.0 december 5, 2011 en avdd vlogic vin uvlo uvlo panel normal operation t ss_vlogic vghm vghm output tied to vgh when vin falls to uvlo voff von vcom vdiv reset 1.280v cd2 1.217v 1.222v 1.215v vdpm gpm enabled when both 1) en = high and 2) vdpm > 1.215v t ss_avdd controlled by v ss figure 19. isl97649a power on/off sequence
isl97649a 19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7928.0 december 5, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl97649a to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change december 5, 2011 fn7928.0 initial release
isl97649a 20 fn7928.0 december 5, 2011 package outline drawing l28.4x5a 28 lead quad flat no-lead plastic package rev 2, 06/08 c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 5.00 (4x) 0.15 6 pin 1 index area 23 pin #1 index area 28 2.50 24x 0.50 exp. dap 8 1 22 14 28x 0.400 9 6 3.50 max 0.90 see detail "x" seating plane 0.08 0.10 c c c ( 4.80 ) ( 3.50 ) ( 28 x 0.60) (28x .250) ( 24x 0.50) ( 3.80 ) ( 2.50) 2.50 0.10 28x 0.25 a mc b 4 3.50 exp. dap 15 typical recommended land pattern detail "x" top view bottom view side view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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